AKD4584 Datasheet, PDF (10/41 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4584

ASAHI KASEI
[AKD4584]
(2) Master Mode
(2-1) A/D evaluation using DIT function of AK4584
Using X’tal (X1), PORT4 (DIT) and J6 (TX). Nothing should be connected to J7 (RX), PORT1 (DIR), PORT5
(DIR) and PORT6 (ROM). The bi-phase data is output from TX3. JP6 (EXT) should be short. In normal speed,
double speed mode and quad speed mode, JP3 (XTI), JP4 (MCLK), JP5 (BCFS) and JP7 (LRFS) should be open.
JP3
JP6
XTI
EXT
JP10
MCLK
JP11
BICK
JP14
LRCK
JP15
SDTI
DIR EXT DIR EXT DIR ADC
• Clock Setting
(2-1-1) Select MCKO1
JP1
MCKO
JP4
MCLK
JP5
BCFS
JP7
LRFS
M1 M2 x1
x2
x4
x1
(2-1-2) Select MCKO2
JP1
MCKO
JP4
MCLK
JP5
BCFS
JP7
LRFS
M1 M2 x1
x2
x4
x1
• SW2 (MODE) setting (See Table 1)
Normal speed and double speed are same setting.
(1) When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down.
(2) When DMCK is “H”, MCKO1 output is disabled.
H 1 2 3 4 5 6 7 8 9 10
L
<KM065800>
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