AK8180B Datasheet, PDF (9/12 Pages) Asahi Kasei Microsystems – 2.5V, 3.3V LVCMOS 1:9 Clock Fanout Buffer

Function Table
The following table shows the inputs/outputs clock state configured through the control pins.
AK8180B
Control Pin
CLK_SEL
OE
CLK_STOP
Table 1: Control-Pin-Setting Function Table
Default
0
1 CCLK0 input selected
1
CCLK1 input selected
1 Outputs disabled. (high impedance) Outputs enabled
1
Outputs synchronously
logic low state.
stopped
in
Outputs active
Application example of CLK_STOP
MS1301-E-00
-9-
May-2011