AK8180B Datasheet, PDF (6/12 Pages) Asahi Kasei Microsystems – 2.5V, 3.3V LVCMOS 1:9 Clock Fanout Buffer

AK8180B
Power Supply Current <2.5V>
Parameter
Full operation ⁽¹⁾
Symbol
IDD1
Conditions
CCLK0=350MHz
CLK_SEL=L
Quiescent state ⁽¹⁾⁽²⁾
IDD2
VDD= 2.5V±5%, Ta: -40 to +85℃
Min
Typ
Max Unit
95
115 mA
0.7
1.3 mA
(1) The outputs have no loads. (2) All inputs are in default state by the internal pull up/down resisters.
DC Characteristics <2.5V>
All specifications at VDD= 2.5V±5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX Unit
High Level Input Voltage
V_IH
LVCMOS
1.7
VDD+0.3 V
Low Level Input Voltage
Input Current ⁽¹⁾
High Level Output Voltage
V_IL
LVCMOS
I_L1
Vin=GND or VDD
V_OH
I_OH= -15mA ⁽²⁾
-0.3
-300
1.8
0.7
V
+300 μA
V
Low Level Output Voltage
V_OL
I_OL= +15mA
0.6
V
Output Impedance
19
W
(1) Input pull-up / pull down resistors influence input current.
(2) The AK8180B is capable of driving 50 W transmission lines of the incident edge. Each output drives one 50 W parallel
terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 W series
terminated transmission lines(for VDD=3.3V) or one 50 W series terminated transmission lines(for VDD=2.5V).
AC Characteristics <2.5V> ⁽¹⁾
All specifications at VDD= 2.5V±5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX Unit
Input Frequency
f_IN
Pin: CCLK
0
350 MHz
Input Pulse Width
t_pwIN
Pin: CCLK
1.4
Input Rise/Fall time ⁽³⁾
t_rIN,t_fOUT Pin: CCLK 0.8 to 2.0V
ns
1.0
ns
Output Frequency
f_OUT
Pin: Q0-8
0
350 MHz
Propagation Delay
t_PLH, t_PHL CCLK to any Q
0.9
1.8
3.6
ns
Output Disable Time
t_PLZ,t_PHZ
11
ns
Output Enable Time
t_PZL,t_PZH
11
ns
Setup Time
t_S
CCLK to CLK_STOP
0.0
ns
Hold Time
t_H
CCLK to CLK_STOP
1.0
ns
Output-to-Output Skew
t_skPP
150
ps
Device-to-Device Skew
t_skD
Output Pulse Skew ⁽⁴⁾
t_skO
CCLK
2.7
ns
200
ps
Output Duty Cycle
DC_OUT DC_REF =50%
45
50
55
%
Output Rise/Fall Time
t_r, t_f
0.6 to 1.8V
0.1
1.0
ns
Cycle-to-Cycle Jitter
t_JITCC
1σ
10
ps
(1) AC characteristics apply for parallel output termination of 50 W to VTT.
(2) Vcmr(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within
the Vcmr range and the input swing lies within the Vpp(AC) specification. Violation of Vcmr or Vpp impacts t_PLH/PHL and t_skD.
(3) Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew,
input pulse width, output duty cycle and maximum frequency specifications.
(4) Output pulse skew t_skO is the absolute difference of the propagation delay times:| t_PLH - t_PHL |.
May-2011
MS1301-E-00
-6-