AK8180B Datasheet, PDF (8/12 Pages) Asahi Kasei Microsystems – 2.5V, 3.3V LVCMOS 1:9 Clock Fanout Buffer

AK8180B
VDD
VDD/2
GND
t_P
T₀
DC = t_P / T₀ x 100%
The time from the PLL controlled edge to the non
controlled edge, divided by the time between PLL
controlled edges, expressed as a percentage.
Figure 5 Output Duty Cycle
VDD=3.3V VDD=2.5V
2.4V
0.55V
1.8V
0.6V
t_F
t_R
Figure 6 Output Translation Test Reference
CCLK
PCLK
CLK_STOPN
t_S
t_H
VDD
VDD/2
GND
VDD
VDD/2
GND
Figure 7 Setup and Hold Time Test Reference
T_N
T_N+1
T_JIT(CC) = | T_N – T_N+1 |
The variation in cycle time of a signal between adjacent
cycles, over a random sample of adjacent cycle pairs.
Figure 8 Cycle-to-Cycle Jitter
May-2011
MS1301-E-00
-8-