AK8136A Datasheet, PDF (9/18 Pages) Asahi Kasei Microsystems – Low Power Multiclock Generator with XO

Function Description
AK8136A
Power On Reset sequence
AK8136A has the POR(Power On Reset) circuit. In power up, the POR works and the register is set to the
initial value and all clock output becomes enable without glitch.
Note1) The assumption power start time to reach 90 % of VDD is within 20 ms.
Note2) The first register setting should be done after the 150 ms elapse after the power on.
VDD1/2/3
VDD*0.9
POR
(Internal signal)
SCL/SDA
CLK1p/CLK2-4/REFOUT
CLK1n
Max:20ms
Min:150ms
Register setting available
Figure.5 Recommend Power Up Sequence
MS1108-E-04
-9-
Dec-2013