AK8136A Datasheet, PDF (12/18 Pages) Asahi Kasei Microsystems – Low Power Multiclock Generator with XO

AK8136A
Register description
The AK8136A generates a range of low-jitter and hi-accuracy clock frequencies with three built-in PLLs and
provides to up to five assigned outputs. A frequency selection at assigned output pin and power down
control is configured by register-setting.
Register Map
Address
FF
FE
D7
FULL_PD
0
CLK4_DIS
0
D6
-
-
CLK3_DIS
0
D5
-
-
CLK2_DIS
0
D4
-
-
CLK1_DIS
0
D3
CLK3S[1]
1
REF_DIS
0
D2
CLK3S[0]
1
D1
CLK2S
0
D0
CLK1S
0
Note
Default
Default
Register definition
FULL_PD (Address FF:D7)
Power Down Control
0
Device Active (PLL ON)
Enable VCXO, VREF and PLLs
1
Full Power Down
Disable VCXO, VREF and PLLs
(default)
Full Power Down sequence
The full power down setting is done by following sequence.
1) Change CLKn_DIS(n=1,2,3,4) and REF_DIS to "1" .
2) Change FULL_PD to "1" from "0".
The output transfers to the disabled state without glitch.
The full power down state is released by following sequence.
1) Changing FULL_PD to "0" from "1" .
2) After more than 4 ms elapse, change CLKn_DIS and REF_DIS
The output transfers to the enable state without glitch.
"0" to "1".
CLKn_DIS,
REF_DIS
FULL_PD
CLK1p/CLK2-4/REFOUT
CLK1n
Figure.6 Full Down sequence
>4ms
Dec-2013
- 12 -
MS1108-E-04