AK8136A Datasheet, PDF (14/18 Pages) Asahi Kasei Microsystems – Low Power Multiclock Generator with XO

AK8136A
REF_DIS (Address FE:D3)
REFOUT Output Disable
0
Enable (REFOUT Active)
1
Disable(REFOUT=”L”)
(default)
Clock Enable and Disable sequence
The enabling and disabling of the clock output are executed without glitch within 500 ns from
the rising edge of SCL during the acknowledge operation after the corresponding byte date
reception.
SCL
SDA
CLKn
REFOUT
Disable
ACK
< 500ns
SCL
SDA
CLKn
REFOUT
Enable
ACK
< 500ns
Figure.7 Output Enable and Disable sequence
Dec-2013
- 14 -
MS1108-E-04