AK8136A Datasheet, PDF (5/18 Pages) Asahi Kasei Microsystems – Low Power Multiclock Generator with XO

AK8136A
AC Characteristics (Clock signals)
VDD: over 3.0 to 3.6V, VDDI over 1.7 to 3.6V,Ta: over -20 to +85℃, 27MHz Crystal, unless otherwise noted
Parameter
Symbol
Conditions
MIN TYP MAX Unit
Crystal Clock Frequency
Output Clock Accuracy
VCXO Pullable Range ⁽¹⁾
Fosc
Faccuracy
PRvcxo
Pin:XI,XO
Pin:CLK2 100.71MHz
Relative to 27.0MHz
VIN at over 0 to VDD V
27.0000
106.25
±150
MHz
ppm
ppm
VCXO Gain
Period Jitter ⁽⁵⁾
Time Interval Error ⁽⁶⁾
Long Term Jitter ⁽⁷⁾
Output Clock Duty
Cycle
Output Clock Slew Rate
Slew rate matching
Differential output swing
Crossing point voltage
Variation of Vcrs
Maximum output voltage
Minimum output voltage
Output Clock Rise Time
Output Clock Fall Time
Output enable/disable Time⁽⁸⁾
Power-up Time 1⁽⁹⁾
Power-up Time 2⁽¹⁰⁾
GVCXO
Jit_period
Jit_tie
Jit_long
DtyCyc
Slew_rise_fall
Slew_ver
V_swing
V_cross
V_cross_delta
V_max
V_min
T_rise
T_fall
T_en_dis
T_put1
T_put2
VIN range at 1.5V±1.0V
Pin:REFOUT⁽²⁾,CLK2-4⁽³⁾
Pin:CLK1⁽⁴⁾
Pin:REFOUT
1000 cycle delay
Pin: CLK1p,n⁽⁴⁾ Figure.3
CLK2-4 ⁽³⁾
45
Pin: REFOUT ⁽²⁾
40
Pin:CLK1p,n ⁽⁴⁾ Figure.3 2.5
Pin:CLK1p,n ⁽⁴⁾ Figure.2
Pin:CLK1p,n ⁽⁴⁾ Figure.3 300
Pin:CLK1p,n ⁽⁴⁾ Figure.2 300
Pin:CLK1p,n ⁽⁴⁾ Figure.2
Pin:CLK1p,n ⁽⁴⁾ Figure.2
Pin:CLK1p,n ⁽⁴⁾ Figure.2 -0.3
Pin: CLK2-4 ⁽³⁾
Pin: REFOUT ^{(2 )}
Pin: CLK2-4 ⁽³⁾
Pin: REFOUT ^{(2 )}
Pin: REFOUT,CLK1p,n
CLK2-4
Pin: REFOUT,CLK1p,n
CLK2-4
Pin: REFOUT,CLK1p,n
CLK2-4
150
150
(6σ)
160
50
50
1.0
2.5
1.0
2.5
ppm/V
ps
100 ps
ps
55 %
60 %
8.0 V/ns
20 %
mV
550 mV
140 mV
1.15 V
V
3.0 ns
5.0 ns
3.0 ns
5.0 ns
500 ns
4
ms
150 ms
(1) Pullable range depends on crystal characteristics, on-chip load capacitance, and stray capacity of PCB.
Typ. ±150ppm is applied to AKM’s authorized test condition.
Please contact us when you plan the use of other crystal unit.
(2) Measured with load capacitance of 25pF
(3) Measured with load capacitance of 15pF
(4) Measured with load condition shown in Figure.1
(5) ±3 in 10000 sampling or more
(6) 16ms accumulate with higher than 10GSa/s.
(7) ±3 in 10000 sampling or more
(8) Refer to Figure.7 on Clock enable and disable sequence.
(9) Time to settle output into 0.1% of specified frequency from FULL_PD is “L”. Refer to Figure.6 on “Full
Power Down sequence”.
(10) Refer to Figure.5 on “Power on Reset sequence”.
MS1108-E-04
-5-
Dec-2013