AK4528 Datasheet, PDF (9/29 Pages) Asahi Kasei Microsystems – HIGH PERFORMANCE 24BIT 96KHZ AUDIO CODEC

ASAHI KASEI
Parameter
Symbol
min
typ
Control Interface Timing (P/S=“L”)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “L” Time
CSN “­” to CCLK “­”
CCLK “­” to CSN “­”
tCCK
200
tCCKL
80
tCCKH
80
tCDS
40
tCDH
40
tCSW
150
tCSW
150
tCSS
150
tCSH
50
Reset Timing
PDN Pulse Width
(Note 13) tPD
150
RSTADN “­” to SDTO valid
(Note 14) tPDV
516
PDN “­” to SDTO valid
(Note 15) tPDV
516
Note:13. The AK4528 can be reset by bringing PDN “L”.
14. In serial mode, these cycles are the number of LRCK rising from RSTADN bit.
15. In parallel mode, these cycles are the number of LRCK rising from PDN pin.
n Timing Diagram
MCLK
LRCK
BICK
1/fCLK
tCLKH
tCLKL
1/fs
tBCK
tBCKH
tBCKL
[AK4528]
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
1/fs
VIH
VIL
VIH
VIL
VIH
VIL
Clock Timing
MS0011-E-00
-9-
2000/1