AK4528 Datasheet, PDF (17/29 Pages) Asahi Kasei Microsystems – HIGH PERFORMANCE 24BIT 96KHZ AUDIO CODEC

ASAHI KASEI
[AK4528]
In case of parallel mode, both ADC and DAC are powered up with releasing internal reset state when PDN is set to “H”.
Therefore each outputs start to output at once. However the initialization of ADC/DAC, and the fade-in cycle of OATT
(8031/fs) are exist.
Power Supply
PDN pin
ADC Internal State
SDTO
DAC Internal State
OATT
AOUT
External Mute
Example
External clocks
PD INITA
“0”
PD INITD
00H
00H ® 7FH
512/fs
Hi-Z
FI
*
Normal
Output
Normal
7FH
Output
MCLK, LRCK, BICK
PD
INITA
Normal
“0”
Output
PD
INITD
Normal
00H
Hi-Z
*
00H ® 7FH
512/fs
FI
*
7FH
Output
MCLK, LRCK, BICK
· INITA:
· INITD:
· PD:
· FI:
· AOUT:
The clocks can be stopped.
Initializing period of ADC analog section (516/fs).
Initializing period of DAC analog section (512/fs).
Power down state.
Fade in. After exiting power down state, ATT value fades in by 8032/fs cycles.
Some pop noise may occur at “*”.
Figure 8. Reset & Power Down Sequence in Parallel Mode
MS0011-E-00
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