AK4528 Datasheet, PDF (16/29 Pages) Asahi Kasei Microsystems – HIGH PERFORMANCE 24BIT 96KHZ AUDIO CODEC

ASAHI KASEI
[AK4528]
n Power Down & Reset
The ADC and DAC of AK4528 are placed in the power-down mode by bringing a power down pin(PDN)=“L” and each
digital filter is also reset at the same time. The internal register values are initialized by PDN=“L”. This reset should always
be done after power-up.
In case of serial mode, the default value of both control registers for ADC and DAC are in reset state (RSTADN=
RSTDAN = ”0” ), each register sholud be cancelled after doing the needed setting. In case of the ADC, an analog
initialization cycle starts after exiting the power-down or reset state. Therefore, the output data, SDTO becomes available
after 516 cycles of LRCK. In case of DAC, the initialization cycle starts after PDN= “H” or PWVR bit = “1”. The power
down mode can be also controlled by the registers (PWAD, PWDA).
Power Supply
PDN pin
RSTADN(registe
RSTDAN(registe
PW AD(register)
PW DA(register)
PW VR(register)
ADC Internal State
SDTO
DAC Internal State
OATT
AOUT
External Mute
Example
External clocks
PD Reset INITA
Normal
PD INITA
“0”
Output
“0”
PD INITD Reset
Normal
Hi-Z
00H
512/fs
“0”
*
00H ® XXH
FI
*
XXH
Output
Normal
PD
Output
“0”
PD Normal
PD INITD
Normal
00H 00H ® XXH XXH
Hi-Z
FI
*
*
Output
00H 00H ® XXH
512/fs
Hi-Z
FI
*
*
XXH
Output
MCLK, LRCK, BICK
The clocks can be stopped.
· INITA:
· INITD:
· PD:
· XXH:
· FI:
· AOUT:
Initializing period of ADC analog section (516/fs).
Initializing period of DAC analog section (512/fs).
Power down state. In case of PDN= “L”, the contents of all registers are initialized, otherwise hold.
The current value in ATT register.
Fade in. After exiting power down and reset state, ATT value fades in by 8032/fs cycles(max).
Some pop noise may occur at “*”.
Figure 7. Reset & Power down sequence in Serial Mode
MS0011-E-00
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