AK8826 Datasheet, PDF (80/157 Pages) Asahi Kasei Microsystems – HD/SD Multi Format Video Encoder with 3ch DAC

■ Output Synchronization waveform
[AK8826VN]
AK8826 output synchronization waveform on Ysignal at default, however, COLSNCEN-bit of HD Block Control Register
[SubAddress 0x27] can add Synchronization waveform on not only Y-signal but also on PB and Pr signal.
The synchronization waveform on Pb and Pr is same as synchronization waveform on Y-signal.
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HD Block Control Register
Sub Address 0x07
bit 7
bit 6
HDWSS
HDCFLT1
bit 5
HDCFLT0
bit 4
HDYFLT1
bit 3
HDYFLT0
bit 2
Reserved
default Value 0x00
bit 1
bit 0
COLSNCEN HDVRATIO
COLSNCEN-bit
0
1
Function
Sync on Y-signal
Sync on Y, Pb, Pr signal
Y
Y
Pb
No sync-waveform
Pb
Pr
No sync-waveform
Pr
COLSNCEN-bit = 0
COLSNCEN-bit = 1
Fig. 118 525i / 625i / 525p / 625p case
Y
Y
Pb
Pb
no sync waveform
Pr
Pr
no sync waveform
COLSNCEN-bit = 0
Fig. 119 1080i / 720p case
COLSNCEN-bit = 1
MS0972-E-01
80
2008/12