AK8826 Datasheet, PDF (120/157 Pages) Asahi Kasei Microsystems – HD/SD Multi Format Video Encoder with 3ch DAC

■ Delay Function for Input Timing Signal
Input Timing Signal can be delayed by setting Register. Amount of adjustment is +/- 3-clock.
Delay adjustment is controled by Video DAC Delay Control Register [SubAddress0x51].
Video DAC Delay Control Register
Sub Address 0x51
bit 7
bit 6
bit 5
Reserved
Reserved
Reserved
bit 4
Reserved
bit 3
Resrved
bit 2
HDLY2
Amount of Delay is set wit 2’s Compriment.
HDLY[2:0]-bit
Delay
000
Delay 0
001
1CLK Delay
010
2CLK Delay
011
3CLK Delay
111
1CLK Advanced
110
2CLK Advanced
101
3CLK Advanced
[AK8826VN]
default Value 0x00
bit 1
bit 0
HDLY1
HDLY0
MS0972-E-01
120
2008/12