AK4645AEZ Datasheet, PDF (80/85 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP

[AK4645A]
■ ϚΠΫೖྗ࿥Ի εςϨΦ
FS3-0 bits _0,000
(Addr:05H, D5&D2-0)
(1)
MIC Control
(Addr:02H, D2-0)
ALC Control 1
(Addr:06H)
ALC Control 2
(Addr:08H)
001
(2)
00H
(3)
E1H
(4)
ALC Control 3
(Addr:0BH)
ALC Control 4
(Addr:07H)
ALC State
00H
(5)
07H
(6)
ALC Disable
0,010
101
3CH
E1H
00H
21H
ALC Enable
01H
(9)
ALC Disable
PMADL/R bits
(Addr:00H&10H, D0)
ADC Internal
State
Power Down
1059 / fs
(7)
(8)
Initialize Normal State Power Down
Example:
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Pre MIC AMP: +20dB
MIC Power On
ALC setting: Refer to Table 34
ALC bit=“1”
(1) Addr:05H, Data:27H
(2) Addr:02H, Data:05H
(3) Addr:06H, Data:3CH
(4) Addr:08H, Data:E1H
(5) Addr:0BH, Data:00H
(6) Addr:07H, Data:21H
(7) Addr:00H, Data:41H
Addr:10H, Data:01H
Recording
(8) Addr:00H, Data:40H
Addr:10H, Data:00H
(9) Addr:07H, Data:01H
Figure 71. MIC Input Recording Sequence
<खॱྫ>
fs=44.1kHz࣌ͷALCͷઃఆྫͰ͢ɻALCͷύϥϝʔλΛมߋ͢Δ৔߹͸ɺ“Figure 29. ”Λࢀরͯ͠Լ͍͞ɻ
ʮΫϩοΫͷઃఆʯͷ߲Λࢀর͠ɺΫϩοΫΛͯ͠څڙԼ͍͞ɻ
(1) αϯϓϦϯάप೾਺(FS3-0 bits)Λઃఆͯ͠Լ͍͞ɻ
(2) ϚΠΫೖྗ(ΞυϨε 02H)ͷઃఆɻ
(3) ALC Timer (ΞυϨε 06H)ͷઃఆ
(4) ALC REF஋(ΞυϨε 08H)ͷઃఆ
(5) LMTH1, RGAIN1 bitsͷઃఆ(ΞυϨε 0BH)
(6) LMTH0, RGAIN0, LMAT1-0, ALC bitsͷઃఆ(ΞυϨε 07H)
(7) ϚΠΫͼٴADCͷύϫʔΞοϓ : PMADL = PMADR bits = “0” → “1”
ADCͷॳظԽαΠΫϧ͸1059/fs=24ms@fs=44.1kHzͰ͢ɻ
ALC͸ೖྗσΟδλϧϘϦϡʔϜ(IVL/R7-0 bits)ͷॳظ஋(+30dB)͔Βಈ࡞Λ։࢝͠·͢ɻ
ظॳԽαΠΫϧऴྃޙɺΦϑηοτిѹ͕ऩଋ͢Δ·Ͱͷ࣌ؒ͸Ξφϩάೖྗϐϯ͕ίϞϯిѹʹ
ऩଋ͢Δ·Ͱ࣌ؒͱσΟδλϧHPFͷ࣌ఆ਺ʹґଘ͠·͢ɻऩଋ࣌ؒΛ୹ॖ͢Δʹ͸ɺPMVCM bit =
“1”ʹଓ͚ͯPMMP bit = “1”Λઃఆ͠ɺΞφϩάೖྗͷACΧοϓϦϯάίϯσϯαͱ60k(typ)Ͱܾ·
Δ࣌ఆ਺ͷ4ഒܦաޙɺADCΛPower-up͢Δํ๏͕͋Γ·͢ɻ
(8) ϚΠΫͼٴADCͷύϫʔμ΢ϯ: PMADL = PMADR bits = “1” → “0”
ϚΠΫͼٴADCΛύϫʔμ΢ϯ͢Δ͜ͱͰALC΋Disableঢ়ଶʹͳΓ·͢ɻαϯϓϦϯάप೾਺Λม
ߋ͠ɺALCͷઃఆΛมߋ͢Δ৔߹͸ɺϚχϡΞϧϞʔυ(ALC bit = “0”) ͋Δ͍͸ϚΠΫͼٴADCΛύ
ϫʔμ΢ϯ(PMADL = PMADR bits = “0”)͔ͯ͠ΒߦͬͯԼ͍͞ɻ·ͨɺPMADL = PMADR bits = “0”
ͷͱ͖ɺೖྗσΟδλϧϘϦϡʔϜ(IVL/R7-0 bits)ͷήΠϯ͸Ϧηοτ͞Εͣɺ࣍ͷύϫʔΞοϓ࣌
͸ίϯτϩʔϧϨδελͷઃఆ஋Ͱಈ࡞Λ։࢝͠·͢ɻ
(9) ALC Disable: ALC bit = “1” → “0”
MS0986-J-00
- 80 -
2008/07