AK4645AEZ Datasheet, PDF (15/85 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP

[AK4645A]
Parameter
Symbol
min
typ
max
Control Interface Timing (3-wire Serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN Edge to CCLK “↑” (Note 34)
CCLK “↑” to CSN Edge (Note 34)
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
tCCK
200
-
-
tCCKL
80
-
-
tCCKH
80
-
-
tCDS
40
-
-
tCDH
40
-
-
tCSW
150
-
-
tCSS
50
-
-
tCSH
50
-
-
fSCL
-
-
400
tBUF
1.3
-
-
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
-
-
Clock Low Time
tLOW
1.3
-
-
Clock High Time
tHIGH
0.6
-
-
Setup Time for Repeated Start Condition
tSU:STA
0.6
-
-
SDA Hold Time from SCL Falling (Note 35)
tHD:DAT
0
-
-
SDA Setup Time from SCL Rising
tSU:DAT 0.1
-
-
Rise Time of Both SDA and SCL Lines
tR
-
-
0.3
Fall Time of Both SDA and SCL Lines
tF
-
-
0.3
Setup Time for Stop Condition
tSU:STO
0.6
-
-
Capacitive Load on Bus
Cb
-
-
400
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
-
50
Power-down & Reset Timing
PDN Pulse Width (Note 36)
tPD
150
-
-
PMADL or PMADR “↑” to SDTO valid (Note 37)
tPDV
-
1059
-
Note 33. I²C͸Philips Semiconductorsͷొ࿥঎ඪͰ͢ɻ
Note 34. ͜ͷ֨ن஋͸CSNͷΤοδͱCCLKͷ “↑”͕ॏͳΒͳ͍Α͏ʹنఆ͍ͯ͠·͢ɻ
Note 35. σʔλ͸࠷௿300ns (SCLͷཱͪԼ͕Γ࣌ؒ)ͷؒอ࣋͞Εͳ͚Ε͹ͳΓ·ͤΜɻ
Note 36. AK4645A͸PDN pin = “L”ͰϦηοτ͞Ε·͢ɻ
Note 37. PMADL bit·ͨ͸PMADR bitΛ্ཱ͔ͪ͛ͯΒͷLRCKΫϩοΫͷ “↑”ͷճ਺Ͱ͢ɻ
Units
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
ns
1/fs
MS0986-J-00
- 15 -
2008/07