AKD4702 Datasheet, PDF (8/32 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4702

ASAHI KASEI
[AKD4702]
n DIP-switch (S1) List
No. Switch Name
1
CM0
2
DIF0
3
DIF2
4
-
5
-
Default
OFF
OFF
OFF
OFF
OFF
Function
Refer the “n Evaluation mode”
(Reserved)
(Reserved)
Table 4. DIP-switch list
n Jumper List
No. Jumper Name
Function
MCLK source set-up when CM0=”H”.
1 EXT
Short: X’tal (default).
Open: External clock via BNC (J1). Remove the on-board X’tal.
Clock source set-up
2,3, MCLK, BICK,
4,5 LRCK, SDTI
Short: Connect the DIR (AK4112B). (default)
Open: Separate the DIR. Supply clocks via Port1.
6 RX
S/PDIF’s port set-up when CM0=”L”.
TORX: Optical connector PORT2. (default)
BNC: BNC connector J2.
Analog ground and digital ground
7 GND
Open: separated (default).
Short: connected (The connector “DGND” can be open.).
Power supply source set-up for digital section of AKD4702.
8 D-A
Open: from the “D5V” Jack. (default)
Short: from the regulator or the “+5V” Jack. Don’t connect anything to the “D5V” Jack.(default)
Power supply source set-up for VD of AK4702.
9 REG
Open: from the “+5V” Jack.
Short: from the regulator. Don’t connect anything the “+5V” Jack. (default)
Power supply source set-up for VVD1 of AK4702.
10 VVD1
Open: from the “VVD1” Jack.
Short: from the regulator or the “+5V” Jack. Don’t connect anything to the “VVD1” Jack. (default)
11 VVD2
12 VCRRC
Power supply source set-up for VVD1 of AK4702.
Open: from the “VVD2” Jack.
Short: from the regulator or the “+5V” Jack. Don’t connect anything to the “VVD2” Jack. (default)
Input Selection for VCRRC
“I” side: Input to VCRRC from VCRRC jack.
“I/O” side: Input to VCRC from VCRC jack.
(Note: Refer CIO bit of AK4702)
Table 5. Jumper list
<KM067304>
-8-
2002/12