AKD4702 Datasheet, PDF (6/32 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4702

ASAHI KASEI
[AKD4702]
2) On-board X’tal mode/ Feeding external MCLK via BNC
When the CM0 (DIP-switch S1_1 on board) is “H”, the AK4112B generates MCLK, BICK and LRCK from
on-board X’tal or external clock form J1. SDATA should be fed via PORT1.
2)-1. DIP-switch set-up
No. CM0
DIF1
DIF0
1
“H”
Don’t care Don’t care
Table 2. DIP-switch set-up
2)-2. Jumper pins set up
2)-2-a. Using on-board X’tal
JP1
JP2
EXT
MCLK
JP3
BICK
JP4
SDTI
JP5
LRCK
JP6: Don’t care.
2)-2-b. Using external clock via BNC connector J1
JP1
JP2
JP3
EXT
MCLK
BICK
JP4
SDTI
JP5
LRCK
JP6: Don’t care.
Remove the on-board X’tal.
<KM067304>
-6-
2002/12