AKD4702 Datasheet, PDF (7/32 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4702

ASAHI KASEI
[AKD4702]
3) Feeding all clocks from external
Under the following set-up, all external signals can be fed to AK4702 through POTR1 (EXT).
The AKM’s evaluation board for ADC can be used.
3)-1. DIP-switch set-up
No. CM0
DIF1
DIF0
1 Don’t care Don’t care Don’t care
Table 3. DIP-switch set-up
3)-2. Jumper pins set up
JP1
EXT
JP2
MCLK
JP3
BICK
JP4
SDTI
JP5
LRCK
JP6: Don’t care.
n Other jumper pins set up
[JP12](VCRRC): Input Jack selection for the VCRRC pin of AK4702
When the VCRC pin of AK4702 outputs 0V by setting CIO bit to “1”, the signal can be fed through the
J27 (VCRCOUT) to VCRRC pin.
“I”: The signal is fed through the J18(VCRRC) to VCRRC pin. (Default)
“I/O”: The signal is fed through the J27(VCRCOUT) to VCRRC pin. The CIO bit of AK4702 should be
set to “1”.
[JP7](GND): Analog ground and digital ground
Open: separated. (Default)
Short: connected. (The jack “DGND” can be open.)
JP7
DGND AGND
<KM067304>
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2002/12