AK8181H Datasheet, PDF (8/12 Pages) Asahi Kasei Microsystems – 2.5V, 3.3V LVPECL 1:10 Clock Fanout Buffer

AK8181H
Function Table
The following table shows the inputs/outputs clock state configured through the control pins.
Inputs
PCLK0/1p
0
1
0
1
Biased ⁽¹⁾
Biased ⁽¹⁾
PCLK0/1n
1
0
Biased ⁽¹⁾
Biased ⁽¹⁾
0
1
Table 1: Control Input Function Table
Outputs
Q0:Q9
Q0n:Q9n
Input to Output
Low
High
Differential to Differential
High
Low
Differential to Differential
Low
High
Single Ended to Differential
High
Low
Single Ended to Differential
High
Low
Single Ended to Differential
Low
High
Single Ended to Differential
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
Inverting
(1) Please refer to the application Information section, “Wiring the Differential Input to Accept Single Ended
Levels”.
Table 2 Clock Input Function Table
CLK_SEL
0
1
Inputs
Selected Source
PCLK0p/n
PCLK1p/n
Feb-2013
draft-E-02
-8-