AK8181H Datasheet, PDF (2/12 Pages) Asahi Kasei Microsystems – 2.5V, 3.3V LVPECL 1:10 Clock Fanout Buffer

AK8181H
Pin Descriptions
Package: 32-Pin LQFP(Top View)
Pin No.
1, 9, 16,
25, 32
2
3
4
5
6
7
8
Pin Name
VDD
CLK_SEL
PCLK0p
PCLK0n
nc
PCLK1p
PCLK1n
VSS
Pin
Type
Pullup
down
Description
PWR
---
Positive power supply
IN
IN
IN
IN
IN
PWR
Pull down
CLK Select Input (LVCMOS/LVTTL)
Pin is connected to VSS by internal resistor. (typ. 51kΩ
High: selects PCLK1p/n inputs
Low (Open): selects PCLK0p/n inputs
Non-inverting differential clock input
Pull down
Pin is connected to VSS by internal resistor. (typ. 51kΩ
*When using PCLK1 input (CLK_SEL=High), it should be
connected to VSS or opened.
Inverting differential clock input
Pull up
Pin is connected to VDD by internal resistor. (typ. 51kΩ
*When using PCLK1 input (CLK_SEL=High), it should be
connected to VDD or opened.
---
No connect
Non-inverting differential LVPECL clock input
Pull down ^{Pin is connected to VSS by internal resistor. (typ. 51kΩï€} 
*When using PCLK0 input (CLK_SEL=Low), it should be
connected to VSS or opened.
Inverting differential clock input
Pull up
Pin is connected to VDD by internal resistor. (typ. 51kΩ
*When using PCLK0 input (CLK_SEL=Low), it should be
connected to VDD or opened.
---
Negative power supply
Feb-2013
draft-E-02
-2-