AK4426 Datasheet, PDF (8/28 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

[AK4426]
DC CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V)
Parameter
Symbol
min
typ
max Units
High-Level Input Voltage
VIH
2.2
-
-
V
Low-Level Input Voltage
VIL
-
-
0.8
V
Input Leakage Current
Iin
-
-
± 10
μA
SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V)
Parameter
Symbol min
Typ
Master Clock Frequency
Duty Cycle
fCLK
dCLK
2.048
30
11.2896
LRCK Frequency
Normal Speed Mode
fsn
8
Double Speed Mode
fsd
32
Quad Speed Mode
fsq
120
Duty Cycle
Duty
45
Audio Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 14)
LRCK Edge to BICK “↑” (Note 14)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128f
sn
1/64fs
d
1/64fs
q
30
30
20
20
20
20
Control Interface Timing (I2C Bus) (Note 15)
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA 0.6
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH 0.6
Setup Time for Repeated Start Condition
tSU:STA 0.6
SDA Hold Time from SCL Falling (Note 16) tHD:DAT 0
SDA Setup Time from SCL Rising
tSU:DAT 0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO 0.6
Pulse Width of Spike Noise
tSP
0
Suppressed by Input Filter
Capacitive load on bus
Cb
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. I²C-bus is a trademark of NXP B.V.
Note 16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
max
36.864
70
48
96
192
55
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
Units
MHz
%
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
MS1176-E-02
-8-
2011/03