AK4426 Datasheet, PDF (19/28 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

[AK4426]
■ Mode Control Interface
I²C-bus Control Mode
1. WRITE Operations
Figure 13 shows the data transfer sequence in I²C-bus mode. All commands are preceded by START condition. A HIGH
to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 17). After the START
condition, a slave address is sent. This address is 7 bits long followed by the eighth bit which is a data direction bit (R/W).
The most significant six bits of the slave address are fixed as “001000”. The next bit is CAD0 (device address bit). This
bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets this device address bit (Figure 14).
If the slave address match that of the AK4426 and R/W bit is “0”, the AK4426 generates an acknowledge and the write
operation is executed. If R/W bit is “1”, the AK4426 does not answer any acknowledge (Figure 17). The second byte
consists of the address for control registers of the AK4426. The format is MSB first, and those most significant 6-bits are
fixed to zeros (Figure 15). The data after the second byte contain control data. The format is MSB first, 8bits (Figure 16).
The AK4426 generates an acknowledge after each byte is received. A data transfer is always terminated by STOP
condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP
condition (Figure 17).
The AK4426 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4426
generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address
counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 04H prior
to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 19) except for the START and the STOP
condition.
SDA
S
T
A
R/W= “0”
R
T
S
Slave
Address
Sub
Address(n)
Data(n)
Data(n+1)
A
A
A
A
C
C
C
C
K
K
K
K
Figure 13. Data Transfer Sequence at I²C-bus Mode
S
T
O
P
Data(n+x) P
A
A
C
C
K
K
0
0
1
0
0
0 CAD0 R/W
Figure 14. The First Byte (The CAD0 should match with CAD0 pin)
0
0
0
0
0
0
A1
A0
Figure 15. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 16. Byte Structure After The Second Byte
MS1176-E-02
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2011/03