AK4426 Datasheet, PDF (18/28 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output

[AK4426]
■ Reset Function
When the MCLK, LRCK or BICK stops, the AK4426 is placed in reset mode and its analog outputs are set to VSS (0V,
typ). When the MCLK, LRCK and BICK are restarted, the AK4426 returns to normal operation mode.
Clock In
MCLK, BICK, LRCK
Internal
State
D/A In
(Digital)
D/A Out
(Analog)
Normal Operation
(1)
MCLK or BIC K or LRCK
Sto p
Reset
Normal Operation
(2)
(4)
VSS
(4)
GD (3)
Notes:
(1) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped).
(2) Digital data can be stopped. The click noise after MCLK and LRCK are input again can be reduced by inputting
the “0” data during this period.
(3) The analog output corresponding to a specific digital input has group delay (GD).
(4) No audible click noise occurs under normal conditions.
Figure 12. Reset Timing Example
MS1176-E-02
- 18 -
2011/03