AK4359_06 Datasheet, PDF (8/33 Pages) Asahi Kasei Microsystems – 106dB 192kHz 24-Bit 8ch DAC

ASAHI KASEI
[AK4359]
SWITCHING CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.5 ∼ 5.5V; C_L = 20pF)
Parameter
Symbol
Min
Master Clock Frequency
Duty Cycle
fCLK
dCLK
2.048
40
LRCK Frequency
Normal Mode (TDM0= “0”, TDM1= “0”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
TDM256 mode (TDM0= “1”, TDM1= “0”)
Normal Speed Mode
High time
Low time
TDM128 mode (TDM0= “1”, TDM1= “1”)
Normal Speed Mode
Double Speed Mode
High time
Low time
Audio Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 14)
LRCK Edge to BICK “↑” (Note 14)
SDTI Hold Time
SDTI Setup Time
Control Interface Timing (3-wire Serial control mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 15)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
fsn
fsd
fsq
Duty
fsn
tLRH
tLRL
fsn
fsd
tLRH
tLRL
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
8
60
120
45
8
3/256fs
3/256fs
8
60
3/128fs
3/128fs
81
30
30
20
20
10
10
200
80
80
40
40
150
50
50
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
Typ
11.2896
Max
36.864
60
48
96
192
55
48
48
96
400
-
-
-
-
-
-
-
0.3
0.3
-
50
Units
MHz
%
kHz
kHz
kHz
%
kHz
ns
ns
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
MS0289-E-02
-8-
2006/03