AK4359_06 Datasheet, PDF (18/33 Pages) Asahi Kasei Microsystems – 106dB 192kHz 24-Bit 8ch DAC

ASAHI KASEI
[AK4359]
„ De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs). In case of double speed and
quad speed mode, the digital de-emphasis filter is always off. In serial control mode, the DEM0-1 bits are valid for the
DAC enabled by the DEMA-D bits. In parallel control mode, DEM0-1 pins are valid.
DEM1
0
0
1
1
DEM0
0
1
0
1
Mode
44.1kHz
OFF
48kHz
32kHz
Default
Table 11. De-emphasis Filter Control (Normal Speed Mode)
„ Output Volume
The AK4359 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition
time of 1 level and all 256 levels is shown in Table 12. The attenuation level is calculated by ATT = 20 log₁₀
(ATT_DATA / 255) [dB] and MUTE at ATT_DATA = “0”.
Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Transition Time
1 Level
255 to 0
4LRCK
1020LRCK
8LRCK
2040LRCK
16LRCK
4080LRCK
„ Zero Detection
Table 12. ATT Transition time
When the input data at all channels are continuously zeros for 8192 LRCK cycles, the AK4359 has Zero Detection like
Table 13. DZF pin immediately goes to “L” if input data of each channel is not zero after going DZF “H”. If RSTN bit is
“0”, DZF pin goes to “H”. DZF pin goes to “L” after 4~5LRCK if input data of each channel is not zero after RSTN bit
returns to “1”. Zero detect function can be disabled by DZFE bit. In this case, all DZF pins are always “L”. When one of
PW1-4 bit is set to “0”, the input data of DAC that the PW bit is set to “0” should be zero in order to enable zero detection
of the other channels. When all PW1-4 bits are set to “0”, DZF pin fixes “L”. DZFB bit can invert the polarity of DZF pin.
In parallel control mode, the zero detect function is disabled and the DZF pin is fixed to “L”.
DZF Pin
DZF1
DZF2
Operations
ANDed output of zero detection flag of each channel set to “1” in 0CH register
ANDed output of zero detection flag of each channel set to “1” in 0DH register
Table 13. DZF pins Operation
MS0289-E-02
- 18 -
2006/03