AK1543 Datasheet, PDF (8/35 Pages) Asahi Kasei Microsystems – 1300MHz Delta-Sigma FractionalSigma -N Frequency Synthesizer

[AK1543]
2. Serial Interface Timing
<Write-In Timing>
LE
(Input)
CLK
(Input)
DATA
(Input)
Tsu Thd
D19
D18
Tch Tcl
Tlesu ^Tle Tcsu
D0
A3
A2
A1
A0
D19
Fig. 3 Serial Interface Timing
Table 5 Serial Interface Timing
Parameter
Symbol Min.
Typ.
Max. Unit
Remarks
Clock L level hold time
Tcl
40
ns
Clock H level hold time
Tch
40
ns
Clock setup time
Tcsu
20
ns
Data setup time
Tsu
20
ns
Data hold time
Thd
20
ns
LE Setup Time
Tlesu
20
ns
LE Pulse Width
Tle
40
ns
Note 1) LE pin has to be set “Low” after register data setting completed. If LE pin keeps “High” with CLK operation, the
register may not be guaranteed proper setting.
Note 2) While LE pin is setting “Low”, 24 iteration clocks have to be set with CLK pin. If 25 or larger clocks are set, the
last 24 clocks synchronized data are valid.
MS1206-E-02
8
2013/03