AK1543 Datasheet, PDF (15/35 Pages) Asahi Kasei Microsystems – 1300MHz Delta-Sigma FractionalSigma -N Frequency Synthesizer

[AK1543]
4.2 Digital Lock Detect
{LD} in <Address3> is set to “0
{LDCKSEL[1:0]} in <Address3> is set to “00”
In the digital lock detect, the [LD] pin outputs is ”Low” every time when the frequency is set. And the [LD] pin outputs is
“High” (which means the locked state) when a phase error smaller than T is detected for 63 times consecutively. If the
phase error is larger than T is detected for N times consecutively then the [LD] pin outputs is “High” and then the [LD] pin
outputs is “Low”(which means the unlocked state).
LDCKSEL=0
Reference clock
PFD clock
VCO divide clock
Phase detector output
Lock detect result
ï¼´
Invalid _Valid
Valid
Valid
Invalid
Invalid ^Valid
Fig. 8 Digital Lock Detect Operation
MS1206-E-02
15
2013/03