AK1543 Datasheet, PDF (17/35 Pages) Asahi Kasei Microsystems – 1300MHz Delta-Sigma FractionalSigma -N Frequency Synthesizer

[AK1543]
5. Reference Input
The reference input can be set with a dividing number in the range of 4 to 255 using {R[7:0]}, which is a 8-bit address in
<Address3>. A dividing number from 0 to 3 cannot be set.
6. Prescaler and Swallow Counter
The dual modular prescaler (P/P + 1) and the swallow counter are used to provide a large dividing ratio.
The prescaler is set by {PRE[1:0]}, which is a 2-bit address in <Address3>.
When {PRE[1:0]} =”00” or ”01”, P = 8 is selected and then an integer from 201 to 16383 can be set.
When {PRE[1:0]} =”10” or “11”, P = 16 is selected and then an integer from 521 to 32767 can be set.
For details of how to calculate an integer, see the section “Frequency Setup” in “8. Block Functional Description”.
7. Power Save Mode
The AK1543 can be operated in the power-down or power-save mode as necessary by using the external control pins
[PDN1] and [PDN2].
○ Power On
See “13. Power-up Sequence”. It is necessary to bring [PDN1] to “High” first, then [PDN2]. Bringing [PDN1] and [PDN2] to
“High” simultaneously is prohibited.
○ Normal Operation
Pin name
PDN1
PDN2
State
“Low”
“Low” Power down
“Low”
“High” Prohibited
“High”
“Low” Power save Note 1) and Note 2)
“High” “High” Normal Operation
Note 1) Register setup can be made 50us after [PDN1] is set to “High”. The charge pump is in the Hi-Z state.
Note 2) Register settings are maintained when [PDN2] is set to “Low” during normal operation.
MS1206-E-02
17
2013/03