AK8181E Datasheet, PDF (7/10 Pages) Asahi Kasei Microsystems – 3.3V LVPECL 1:4 Clock Fanout Buffer

Function Table
The following table shows the inputs/outputs clock state configured through the control pins.
AK8181E
CLK_EN
0
0
1 (Open)
1 (Open)
Table 1: Control Input Function Table
Inputs
CLK_SEL
0 (Open)
1
0 (Open)
1
Selected Source
PCLKp/n
XTAL
PCLKp/n
XTAL
Outputs
Q0:Q3
Q0n:Q3n
Disabled: Low
Disabled: High
Disabled: Low
Disabled: High
Enabled
Enabled
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or
crystal oscillator edge as shown in Figure 7. In the active mode, the state of the outputs are a function of the
PCLKp/n and XTAL inputs as described in Table 2.
Figure 7 CLK_EN Timing Diagram
Inputs
PCLKp
0
PCLKn
1
1
0
1
Biased ⁽¹⁾
Biased ⁽¹⁾
0
Biased ⁽¹⁾
Biased ⁽¹⁾
0
1
Table 2 Clock Input Function Table
Outputs
Q0:Q3
Q0n:Q3n
Input to Output
Low
High
Differential to Differential
High
Low
Differential to Differential
Low
High
Single Ended to Differential
High
Low
Single Ended to Differential
High
Low
Single Ended to Differential
Low
High
Single Ended to Differential
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
Inverting
(1) Please refer to the application Information section, “Wiring the Differential Input to Accept Single Ended
Levels”.
draft-E-01
-7-
Feb-2013