AK8181E Datasheet, PDF (5/10 Pages) Asahi Kasei Microsystems – 3.3V LVPECL 1:4 Clock Fanout Buffer

AK8181E
AC Characteristics
All specifications at VDD= 3.3V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN TYP MAX Unit
Output Frequency
fOUT
650 MHz
Propagation Delay ⁽¹⁾
Output Skew ^{(2) (3)}
Part-to-Part Skew ^{(3) (4)}
tPD
tsk(O)
tskPP
0.9
ns
10
ps
150 ps
Buffer Additive Jitter, RMS ⁽⁵⁾
PCLKp/n 156.25MHz
(12kHz – 20MHz)
tjit
XTAL 50MHz
(12kHz – 20MHz)
0.04
ps
0.14
ps
Output Rise/Fall Time ⁽⁵⁾
tr, tf
20% to 80%
200
600 ps
Output Duty Cycle
DCOUT PCLKp/n
50
%
All parameters measured at f ≤ 650MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
(1) Measured from the differential input crossing point to the differential output crossing point.
(2) Defined as skew between outputs at the same supply voltage and with equal load conditions.
(3) This parameter is defined in accordance with JEDEC Standard 65.
(4) Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
(5) Design Value
Crystal Characteristics
All specifications at VDD= 3.3V5%, VSS=0V, Ta: -40 to +85°C, unless otherwise noted
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Conditions
MIN
TYP
MAX
Fundamental
12
50
50
7
1
Unit
MHz
Ω
pF
mW
draft-E-01
-5-
Feb-2013