AK8181E Datasheet, PDF (4/10 Pages) Asahi Kasei Microsystems – 3.3V LVPECL 1:4 Clock Fanout Buffer

AK8181E
DC Characteristics (LVCMOS/LVTTL)
All specifications at VDD= 3.3V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Input High Voltage
Input Low Voltage
Input High Current
CLK_SEL
CLK_EN
Input Low Current
CLK_SEL
CLK_EN
Symbol
Conditions
VIH
VIL
Vin=VDD=3.465V
IH
Vin=VDD=3.465V
Vin=VSS,
VDD=3.465V
IL
Vin=VSS,
VDD=3.465V
MIN
2.0
-0.3
-5
-150
TYP
MAX Unit
VDD+0.3 V
0.8
V
150
μA
5
μA
μA
μA
DC Characteristics (Differential)
All specifications at VDD= 3.3V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
Input High Current
PCLKp
PCLKn
Vin=VDD=3.465V
IH
Vin=VDD=3.465V
Input Low Current
PCLKp
PCLKn
Vin=VSS,
VDD=3.465V
IL
Vin=VSS,
VDD=3.465V
-5
-150
Peak-to-Peak Input Voltage
VPP
0.15
Common Mode Input Voltage ^{(1) (2)}
VCMR
VSS+0.5
(1) For single ended applications, the maximum input voltage for PCLKp and PCLKn is VDD+0.3V.
(2) Common mode voltage is defined as VIH.
MAX Unit
150
μA
5
μA
μA
μA
1.3
V
VDD-0.85 V
DC Characteristics (LVPECL)
All specifications at VDD= 3.3V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Output High Voltage ⁽³⁾
VOH
Output Low Voltage ⁽³⁾
VOL
Peak-to-Peak Output Voltage Swing VSWING
(3) Outputs terminated with 50Ω to VDD-2V.
Conditions
MIN
TYP
MAX Unit
VDD-1.4
VDD-2.0
0.6
VDD-0.9 V
VDD-1.7 V
1.0
V
Feb-2013
draft-E-01
-4-