AK8181E Datasheet, PDF (2/10 Pages) Asahi Kasei Microsystems – 3.3V LVPECL 1:4 Clock Fanout Buffer

AK8181E
Pin Descriptions
Package: 20-Pin TSSOP(Top View)
Pin No.
1
2
3
4
5
6
7
8,
9
10
11, 12
13
14, 15
16, 17
18
19, 20
Pin Name
VSS
Pin
Type
PWR
CLK_EN
IN
CLK_SEL IN
PCLKp
IN
PCLKn
IN
XTAL_IN
XTAL_OUT
NC
NC
VDD
Q3n, Q3
VDD
Q2n, Q2
Q1n, Q1
VDD
Q0n, Q0
IN
IN
--
--
PWR
OUT
PWR
OUT
OUT
PWR
OUT
Pullup
Down
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Pull up
Pull down
Pull down
Pull up
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Description
Negative power supply
Synchronizing clock output enable (LVCMOS/LVTTL)
Pin is connected to VDD by internal resistor. (typ. 51kΩ)
High(Open): clock outputs follow clock input.
Low: Q outputs are forced low, Qn outputs are forced high.
CLK Select Input (LVCMOS/LVTTL)
Pin is connected to VSS by internal resistor. (typ. 51kΩ)
High: selects XTAL inputs
Low(Open): selects PCLKp/n inputs
Non-inverting differential clock input
Pin is connected to VSS by internal resistor. (typ. 51kΩ)
Inverting differential clock input
Pin is connected to VDD by internal resistor. (typ. 51kΩ)
Crystal oscillator interface
Crystal oscillator interface
No connect
No connect
Positive power supply
Differential clock output (LVPECL)
Power supply
Differential clock output (LVPECL)
Differential clock output (LVPECL)
Positive power supply
Differential clock output (LVPECL)
Ordering Information
Part Number
Marking
AK8181E
AK8181E
Shipping
Packaging
Tape and Reel
Package
20-pin TSSOP
Temperature
Range
-40 to 85 °C
Feb-2013
draft-E-01
-2-