AK4532 Datasheet, PDF (7/17 Pages) Asahi Kasei Microsystems – Internet/Network/General Purpose Multimedia Audio CODEC

ASAHI KASEI
[AK4532]
SWITCHING CHARACTERISTICS
(Ta=25 ℃; VA, VD = 5.0V±10%, Cl = 20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing (CMODE=L)
fCLK
1.024 11.2896 12.800 MHz
(CMODE=H)
fCLK
1.536 16.9344 19.2
MHz
Pulse Width Low (CMODE=L)
fCLKL
31.25
ns
(CMODE=H)
fCLKL
23
ns
Pulse Width High (CMODE=L)
fCLKH
31.25
ns
(CMODE=H)
fCLKH
23
ns
LRCK Frequency (Note 1)
fs
4
44.1
50
kHz
Duty Cycle
45
55
%
Serial Interface Timing
SCLK Period
tSCK
312.5
ns
SCLK Pulse Width Low
tSCKL
100
ns
SCLK Pulse Width High
tSCKH
100
ns
LRCK Edge to SCLK “rising edge” (Note 2) tLRS
50
ns
SCLK “rising edge” to LRCK edge (Note 2) tSLR
50
ns
SDI Hold Time
tSDH
50
ns
SDI Setup Time
tSDS
50
ns
LRCK to SDO(MSB)
tLRS
70
ns
SCLK “rising edge” to SDO
tSSD
70
ns
Control Interface Timing
CCLK Period
tCCK
200
ns
CCLK Pulse Width Low
tCCKL
80
ns
CCLK Pulse Width High
tCCKH
80
ns
CDATA Hold Time
tCDS
50
ns
CDATA Setup Time
tCDH
50
ns
CS High Level Time
tCSW
150
ns
CS “falling edge” to CCLK “rising” time
tCSS
50
ns
CCLK “rising time” to CS “rising” time
tCSH
50
ns
Reset Timing
PD Pulse Width
tPD
150
ns
PD “rising edge” to SDO delay (Note 3)
tPDS
516
1/fs
Note: 1. If the duty of LRCK changes larger than 5% from 50%, the AK4532 is reset by the internal phase
detecting circuit automatically.
2. SCLK rising edge must not occur at the same time as LRCK edge.
3. These cycles are the number of LRCK rising from PD rising.
0178-E-01
7
1999/06