AK4532 Datasheet, PDF (13/17 Pages) Asahi Kasei Microsystems – Internet/Network/General Purpose Multimedia Audio CODEC

ASAHI KASEI
SDO output is the 16bit data of ADC and goes “L”(0000H) in the following cases.
･ PD pin = “L”
ï½¥ During initializing the analog section(516/fs).
･ RST register = “0”
･ PD register = “0”
4.6. Analog output pin(LOUT, ROUT) operation
These outputs are floating in the following case.
･ PD pin = “L”
･ PD register = “0”
[AK4532]
5. System Clock
The external clocks which are required to operate the AK4532 are MCLK, LRCK and SCLK. MCLK
should be synchronized with LRCK but the phase is free of care. As the AK4532 includes the phase
detect circuit for LRCK, the AK4532 is reset automatically when the synchronization is out of phase
by changing the clock frequencies. Therefore, the reset is not required except only upon power-up.
All external clocks should always be present whenever the AK4532 is in normal operation mode. If these
clocks are not provided, the AK4532 may draw excessive current and do not possibly operate
properly because the device utilizes the dynamic logic internally. If the external clocks are not
present, the AK4532 should be in the power down mode.
5. Digital High Pass Filter
The ADC of the AK4532 has a digital high pass filter for DC offset cancel. The cut-off frequency of
the HPF is 6.85Hz at fs=44.1kHz and the frequency response at 20Hz is -0.5dB. It also scales with
sampling rate(fs).
0178-E-01
13
1999/06