AK4522_12 Datasheet, PDF (7/19 Pages) Asahi Kasei Microsystems – 20Bit Stereo ΔΣ ADC & DAC

ASAHI KASEI
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=4.5 ∼ 5.5V, VD=2.7 ∼ 5.5V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
External Clock 256fs:
fCLK
4.096
Pulse Width Low
tCLKL
27
Pulse Width High
tCLKH
27
384fs:
fCLK
6.144
Pulse Width Low
tCLKL
20
Pulse Width High
tCLKH
20
512fs:
fCLK
8.192
Pulse Width Low
tCLKL
15
Pulse Width High
tCLKH
15
LRCK
Frequency
fsn
16
44.1
Duty Cycle
dfs
45
Serial Interface Timing
Slave mode
SCLK Period
tSCK
160
SCLK Pulse Width Low
tSCKL
65
Pulse Width High
tSCKH
65
LRCK Edge to SCLK “↑”
(Note 13)
tLRS
45
SCLK “↑” to LRCK Edge
(Note 13)
tSLR
45
LRCK to SDTO(MSB)
tLRM
SCLK “↓” to SDTO
tSSD
SDTI Hold Time
tSDH
40
SDTI Setup Time
tSDS
25
Reset Timing
PD Pulse Width
tPD
150
PD “↑” to SDTO valid (Note 14)
tPDV
516
Note 13. SCLK rising edge must not occur at the same time as LRCK edge.
14. These cycles are the number of LRCK rising from PD rising.
The AK4522 can be reset by bringing PD “L”.
[AK4522]
max
12.288
18.432
24.576
48
55
Units
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
kHz
%
ns
ns
ns
ns
ns
40
ns
50
ns
ns
ns
ns
1/fs
M0020-E-02
-7-
2012/01