AK4522_12 Datasheet, PDF (12/19 Pages) Asahi Kasei Microsystems – 20Bit Stereo ΔΣ ADC & DAC

ASAHI KASEI
[AK4522]
„ Power-Down & Reset
The ADC and DAC of AK4522 are placed in the reset mode by bringing a reset pin, PD “L”. This reset should always
be done after power-up. In case of the ADC, an analog initialization cycle starts after exiting the reset mode. Therefore,
the output data, SDTO becomes available after 516 cycles of LRCK clock. This initialization cycle does not affect the
DAC operation. Figure 6 shows the power-up sequence.
PD
ADC Internal
State
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
DAC Out
(Analog)
Clock In
MCLK,LRCK,SCLK
External
Mute
Normal Operation
Normal Operation
GD ⁽²⁾
Reset
Reset
(1)
516/fs
Init Cycle
Normal Operation
Normal Operation
GD
(3)
“0”data
“0”data
(2)
GD
(5)
(5)
(4)
GD
The clocks may be stopped.
(6)
Mute ON
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(3) A/D output is “0” data at the reset state.
(4) Small click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the
click noise influences system application.
(5) Click noise occurs at the edge of PD .
(6) Please mute the analog output externally if the click noise (5) influences system application.
Figure 6. Power-up sequence
M0020-E-02
- 12 -
2012/01