AK4534 Datasheet, PDF (61/64 Pages) Asahi Kasei Microsystems – 16Bit CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4534]
n Stop of Clock
MCLK can be stopped when PMMIC=PMADC=PMDAC=PMSPK= “0”.
1. When X’tal is used in PLL mode
MCKO bit
(Addr:03H, D4)
PMXTL bit
(Addr:01H, D6)
PMPLL bit
(Addr:01H, D5)
MCKPD bit
(Addr:01H, D7)
(1)
(2)
Example :
Audio I/F Form at : I²S
BICK frequency at Master Mode : 64fs
Input Master Clock Select at PLL Mode : 11.2896MHz
Output Master Clock Frequency : 64fs
(1) Addr:04H, Data:62H
(2) Addr:01H, Data:80H
Figure 41. Stop of Clock Sequence(1)
<Example>
(1) Disable MCKO output : MCKO bit = “1” → “0”
(2) Power down X’tal and PLL, Pull down the XTI pin :
PMXTL bit = PMPLL bit = “1” → “0”, MCKPD = “0” → “1”
2. When an external clock is used in PLL mode
MCKO bit
(Addr:03H, D4)
PMPLL bit
(Addr:01H, D5)
MCKPD bit
(Addr:01H, D7)
External MCLK
(1)
(2)
(3)
Input
Example :
Audio I/F : I²S
BICK frequency at Master Mode : 64fs
Input Master Clock Select at PLL Mode : 11.2896MHz
Output Master Clock Frequency : 64fs
(1) Addr:04H, Data:62H
(2) Addr:01H, Data:80H
(3) Stop external clock
Figure 42. Stop of Clock Sequence(2)
<Example>
(1) Stop MCKO output : MCKO bit = “1” → “0”
(2) Power down PLL, Pull down the XTI pin : PMPLL bit = “1” → “0”, MCKPD = “0” → “1”
When the external MCLK becomes Hi-Z or the external MCLK is input by AC couple, MCKI pin should be
pulled down.
(3) Stop an external MCLK
MS0133-E-03
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2003/5