AK4534 Datasheet, PDF (57/64 Pages) Asahi Kasei Microsystems – 16Bit CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4534]
4. When an external clock is used in PLL mode. (Master mode)
MCKPD bit
(Addr:01H, D7)
External MCLK
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:04H, D3)
PS1-0 bits
(Addr:04H, D5-4)
MCKO pin
(1)
(2)
(3)
00
Input
40ms(max)
(4)
XX
(5)
Output
Example :
Audio I/F Format : I²S
BICK frequency at Master Mode : 64fs
Input Master Clo c k S e lect at PLL Mode : 11.2896MHz
O utput Master Clock Frequency : 64fs
(1) Addr:0 1 H , Data:00H
(2) Input external MCLK
(3) Addr:0 1 H , Data 20H
(4) Addr:0 4 H , Data 6AH
(5) MCKO, BICK and LRCK output starts
BICK, LRCK
(Master Mode)
Output
Figure 36. Clock Set Up Sequence(4)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0”
(2) Input an external MCLK
(3) Power-up PLL : PMPLL bit = “0” → “1”
PLL needs 40ms lock time after the PMPLL bit = “0” → “1”.
(4) Enable MCKO output : MCKO bit = “0” → “1” and set up MCKO output frequency (PS1-0 bits)
(5) MCKO, BICK and LRCK are output after PLL lock time.
5. External clock mode
MCKPD bit
(Addr:01H, D7)
FS1-0 bits
(Addr:05H, D6-5)
(1)
(2)
00
(3)
External MCLK
BICK, LRCK
(4)
(Slave Mode)
BICK, LRCK
(5)
(Master Mode)
XX
Input
Example :
Audio I/F Format : I²S
BICK frequency at Master Mode : 64fs
Input Master Clock Frequency : 256fs
O utput Master Clock Frequency : 64fs
(1) Addr:01H, Data:00H
(2) Addr:05H, Data 00H
Input
(3) Input external MCLK
Output
(4) Input BICK and LRCK(Slave)
(5) BICK and LRCK output(Master)
Figure 37. Clock Set Up Sequence(5)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0”
(2) Set up MCLK frequency (FS1-0 bits)
(3) Input an external MCLK
(4) In slave mode, input MCLK, BICK and LRCK.
(5) In master mode, while MCLK is input, BICK and LRCK are output.
MS0133-E-03
- 57 -
2003/5