AK4490EQ Datasheet, PDF (61/68 Pages) Asahi Kasei Microsystems – Premium 32-Bit 2ch DAC

Digital Ground
System
Controller
Analog Ground
[AK4490]
37 NC
38 VCML
39 VREFLL
40 VREFLL
41 VREFHL
42 VREFHL
43 NC
44 AVDD
45 AVSS
46 MCLK
47 DVSS
48 DVDD
AK4490
NC 24
VCMR 23
VREFLR 22
VREFLR 21
VREFHR 20
VREFHR 19
NC 18
ACKS/CAD1 17
DEM1 16
DEM0 15
I2C 14
PSN 13
Figure 39. Ground Layout
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD
respectively. VREFHL/R and VDDL/R are supplied from analog supply in system, and AVDD and DVDD are
supplied from digital supply in system. Power lines of VREFHL/R and VDDL/R should be distributed
separately from the point with low impedance of regulator etc. AVSS, DVSS, VSSL and VSSR must be
connected to the same analog ground plane. Decoupling capacitors for high frequency should be
placed as near as possible to the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the analog output range. The VREFHL/R pin
is normally connected to AVDD, and the VREFLL/R pin is normally connected to VSS1/2/3. VREFHL/R and
VREFLL/R should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to eliminate the
effects of high frequency noise. No load current may be drawn from VCML/R pin. All signals, especially
clocks, should be kept away from the VREFHL/R and VREFLL/R pins in order to avoid unwanted noise
coupling into the AK4490.
3. Analog Outputs
The analog outputs are full differential outputs and 2.8Vpp (typ, VREFHL/R  VREFLL/R = 5V) centered
around VDDR/2 and VDDL/2 voltages. The differential outputs are summed externally, V_AOUT = (AOUT+) 
(AOUT) between AOUT+ and AOUT. If the summing gain is 1, the output range is 5.6Vpp (typ, VREFHL/R
 VREFLL/R = 5V). The bias voltage of the external summing circuit is supplied externally. The input data
format is 2's complement. The output voltage (V_AOUT) is a positive full scale for 7FFFFFH (@24bit) and a
negative full scale for 800000H (@24bit). The ideal V_AOUT is 0V for 000000H(@24bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond the
audio passband. Figure 40 shows an example of external LPF circuit summing the differential outputs by an
op-amp.
Figure 41 shows an example of differential outputs and LPF circuit example by three op-amps.
MS1648-E-03
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2014/11