AK4490EQ Datasheet, PDF (32/68 Pages) Asahi Kasei Microsystems – Premium 32-Bit 2ch DAC

[AK4490]
[2] DSD Mode
The AK4490 has a DSD playback function. The external clocks, which are required in DSD mode, are MCLK
and DCLK. MCLK should be synchronized with DCLK but the phase is not critical. The frequency of MCLK
is set by DCKS bit.
The AK4490 is automatically placed in reset state when MCLK is stopped during a normal operation (PDN pin
=“H”), and the analog output becomes Hi-z state. However, the external clock (DCLK) should not be stopped.
When DCLK is not supplied, the AK4490 may not be able to operate properly because of an over current since
it has a dynamic logic circuit internally. The PDN pin should be set to “L” when stopping the DCLK. When the
reset is released (PDN pin = “L” → “H”), the AK4490 is in power-down state until MCLK and DCLK are
input.
DCKS bit
0
1
MCLK Frequency DCLK Frequency
512fs
64fs/128fs/256fs
768fs
64fs/128fs/256fs
Table 15. System Clock (DSD Mode)
(default)
The AK4490 supports DSD data stream of 2.8224MHz (64fs), 5.6448MHz (128fs) and 11.2896MHz (256fs).
The data sampling speed is selected by DSDSEL1-0 bits.
DSDSEL1 DSDSEL0 DSD data stream
0
0
2.8224MHz (default)
0
1
5.6448MHz
1
0
11.2896MHz
1
1
Reserved
Table 16. DSD Sampling Speed Control
The AK4490 has a Volume bypass function for play backing DSD signal. Two modes are selectable by DSDD
bit. When setting DSDD bit = “1”, the output volume control function is not available.
DSDD
Mode
0
Normal Path (default)
1
Volume Bypass
Table 17. DSD Play Back Mode Control
When DSDD bit = “1”, filter characteristic can be switched between 50kHz and 100kHz by DSDF bit.
DSDD bit
0
0
1
1
DSDF bit
Cut Off Filter
0
50kHz
1
Reserved
0
50kHz
1
150kHz
Table 18. DSD Filter Select
(default)
MS1648-E-03
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2014/11