AK4490EQ Datasheet, PDF (56/68 Pages) Asahi Kasei Microsystems – Premium 32-Bit 2ch DAC

[AK4490]
Addr Register Name
02H Control 3
R(I2C)/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
DP
0
DCKS DCKB MONO DZFB SELLR SLOW
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
SLOW: Slow Roll-off Filter Enable
0: Sharp roll-off filter (default)
1: Slow roll-off filter
SD
SLOW
Mode
0
0
Sharp roll-off filter
0
1
Slow roll-off filter
1
0
Short delay sharp roll off filter (default)
1
1
Short delay slow roll off filter
Table 14. Digital Filter Setting
SELLR: The data selection of L channel and R channel, when MONO mode
0: All channel output R channel data, when MONO mode. (default)
1: All channel output L channel data, when MONO mode.
It is enabled when MONO bit is “1”, and outputs Rch data to both channels when “0”, outputs Lch
data to both channels when “1”.
DZFB: Inverting Enable of DZF
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
DZFE DZFB
Data
DZF-pin
0
-
L
0
1
-
H
not zero
L
0
Zero detect
H
1
not zero
H
1
Zero detect
L
Table 25. Zero Detect Function and DZF Pin Output
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
When MONO bit is “1”, MONO mode is enabled.
DCKB:Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
DP: DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
When D/P bit is changed, the AK4490 should be reset by RSTN bit.
MS1648-E-03
- 56 -
2014/11