AK4490EQ Datasheet, PDF (58/68 Pages) Asahi Kasei Microsystems – Premium 32-Bit 2ch DAC

INVR: AOUTR Output Phase Inverting
0: Disable (default)
1: Enable
INVL: AOUTL Output Phase Inverting
0: Disable (default)
1: Enable
[AK4490]
Addr Register Name
06H Control 5
R(I2C)/W
Default
D7
DDM
R/W
0
D6
DML
R/W
0
D5
DMR
R/W
0
D4
DMC
R/W
0
D3
DMRE
R/W
0
DSDSEL1-0: DSD Sampling Speed Control (See also Control 7 register.)
D2
D1
D0
0
DSDD DSDSEL0
R
R/W
R/W
0
0
0
DSDSEL1 bit DSDSEL0 bit DSD data stream
0
0
2.8224MHz
0
1
5.6448MHz
1
0
11.2896MHz
1
1
Reserved
Table 16. DSD Sampling Speed Control
(default)
DSDD: DSD Play Back Path Control
DSDD
Mode
0
Normal Path (default)
1
Volume Bypass
Table 17. DSD Play Back Mode Control
DMRE:
DSD Mute Release
0: Hold (default)
1: Release Mute
This register is only valid when DDM bit = “1” and DMC bit = “1”. When the AK4490 mutes
DSD data by DDM and DMC bits settings, the mute is released by setting DMRE bit to “1”.
DMC: DSD Mute Control
0: Auto Return (default)
1: Mute Hold (manual return)
This register is only valid when DDM bit = “1”. It selects the mute releasing mode of when the
DSD data level becomes under full-scale after the AK4490 mutes DSD data by DDM bit setting.
DMR/DML
This register outputs detection flag when a full scale signal is detected at DSDR/L channel.
DDM: DSD Data Mute
0: Disable (default)
1: Enable
The AK4490 has an internal mute function that mutes the output when DSD audio data becomes
all “1” or all “0” for 2048 Samples (1/fs). DDM bit controls this function.
MS1648-E-03
- 58 -
2014/11