AK4458VN Datasheet, PDF (61/83 Pages) Asahi Kasei Microsystems – 115dB 768kHz 32-bit 8ch Premium DAC

[AK4458]
(3) Reset Function (MCLK Stop)
When the MCLK stops for more than 10us during operation (PDN pin = “H”), the AK4458 is placed in reset
state and the analog output goes to floating state (Hi-Z). When the MCLK is restarted, reset state is released
and the AK4458 returns to normal operation mode. Zero detection function is disabled while the MCLK is
stopped. Figure 61 shows a reset sequence by stopping the MCLK.
PDN pin
RSTN bit
(1)
Internal
State
Power-down
Normal Operation
Digital Circuit Power-down
Normal Operation
D/A In
(Digital)
D/A Out
(Analog)
Clock In
MCLK
Power-down
Hi-Z
(4)
GD (2)
(3)
GD (2)
(4)
(4)
MCLK Stop
External
MUTE
(5)
(5)
(5)
Notes:
(1) After the AK4458 is powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) The digital data input can be stopped. Click noise after MCLK is input again can be reduced by
inputting “0” data during this period.
(4) Click noise occurs within 3 ~ 4LRCK from the riding edge (“↑”) of the PDN pin or MCLK inputs. This
noise is output even if “0” data is input.
(5) Mute the analog output externally if click noise (4) adversely affect system performance.
Figure 61. Reset Sequence Example 2
014011794-E-00
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2015/01