AK4458VN Datasheet, PDF (20/83 Pages) Asahi Kasei Microsystems – 115dB 768kHz 32-bit 8ch Premium DAC

[AK4458]
Parameter
Symbol Min. Typ. Max. Unit
DSD Audio Interface Timing
(64 mode, DSDSEL 1-0 bits = “00”)
DCLK Period
tDCK
1/64fs
nsec
DCLK Pulse Width Low
tDCKL 144
nsec
DCLK Pulse Width High
tDCKH 144
nsec
DCLK Edge to DSDL/R (Note 29) ^tDDD
20
20
nsec
(128 mode, DSDSEL 1-0 bits = “01”)
DCLK Period
tDCK
1/128fs
nsec
DCLK Pulse Width Low
tDCKL
72
nsec
DCLK Pulse Width High
tDCKH
72
DCLK Edge to DSDL/R (Note 29) ^tDDD
10
nsec
10
nsec
(256 mode, DSDSEL 1-0 bits = “10”)
DCLK Period
tDCK
1/256fs
nsec
DCLK Pulse Width Low
tDCKL
36
nsec
DCLK Pulse Width High
tDCKH
36
nsec
DCLK Edge to DSDL/R (Note 29) ^tDDD
5
5
nsec
Note 24. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4458 should be
reset by the PDN pin or RSTN bit.
Note 25. BICK rising edge must not occur at the same time as LRCK edge.
Note 26. fsd (max) = 96kHz when TVDD < 3.0V in Daisy Chain mode.
Note 27. fsd (max) = 48kHz when TVDD < 3.0V in Daisy Chain mode.
Note 28. tBSH (min) = 4 nsec when TVDD < 2.6V and the LDOE pin = “L”.
Note 29. DSD data transmitting device must meet this time.
tDDD is defined from a falling edge of DCLK “↓” to a DSDL/R edge when DCKB bit = “0” and it
is defined from a rising edge of DCLK “↑” to a DSDL/R edge when DCKB bit = “1”.
014011794-E-00
- 20 -
2015/01