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AK4645 Datasheet, PDF (60/96 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP | |||
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ASAHI KASEI
[AK4645]
 Full-differential Mono Line Output (LOP/LON pins)
When LODIF bit = â1â, LOUT/ROUT pins become LOP/LON pins, respectively. Lch/Rch signal of DAC or
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the LOP/LON pins which is full-differential as (L+R)/2 signal. The
load impedance is 10k⦠(min) for LOP and LON pins, respectively. When the PMLO bit = â0â, the mono line output
enters power-down mode and the output is Hi-Z. When the PMLO bit is â1â and LOPS bit is â1â, mono line output enters
power-save mode. Pop noise at power-up/down can be reduced by changing PMLO bit at LOPS bit = â0â. When PMLO
bit = â1â and LOPS bit = â0â, mono line output enters in normal operation. LOVL bit set the gain of mono line output.
When L4DIF=LODIF bits = â1â, full-differential output signal is as follows: (LOP) â (LON) = (IN4+) â (IN4â).
DAC
âDACLâ
âLOVLâ
LOP pin
LON pin
PMLO
0
1
Figure 52. Mono Line Output
LOVL
0
1
Gain
Output Voltage (typ)
+6dB
1.2 x AVDD
Default
+8dB
1.5 x AVDD
Table 52. Mono Line Output Volume Setting
LOPS
Mode
LOP
LON
x
Power-down
Hi-Z
Hi-Z
1
Power-save
Hi-Z
VCOM/2
0
Normal Operation Normal Operation Normal Operation
Table 53. Mono Line Output Mode Setting (x: Donât care)
Default
PMLO bit
LOPS bit
LOP pin
Hi-Z
Hi-Z
LON pin Hi-Z
VCOM
VCOM
Hi-Z
Figure 53. Power-up/Power-down Timing for Mono Line Output
MS0543-E-00
- 60 -
2006/09
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