AK4645 Datasheet, PDF (56/96 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP

ASAHI KASEI
[AK4645]
„ Stereo Line Output (LOUT/ROUT pins)
When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When
DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ
(min.). When the PMLO=LOPS bits = “0”, the stereo line output enters power-down mode and the output is pulled-down
to AVSS by 2Ω(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at power-up/down
can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be pulled-down to AVSS
by 20kΩ after AC coupled as Figure 46. Rise/Fall time is 300ms(max) at C=1µF and AVDD=3.3V. When PMLO=LOPS
bits = “1”, stereo line output is in normal operation.
LOVL bit set the gain of stereo line output.
When LOM bit = “1”, DAC output signal is output to LOUT and ROUT pins as (L+R)/2 mono signal.
When LOM3 bit = “1”, the signal selected by MICL3 and MICR3 bits (LIN3/RIN3 inputs or MIC-Amp outputs) to
LOUT and ROUT pins as (L+R)/2 mono signal.
DAC
“DACL”
“LOVL”
LOUT pin
ROUT pin
LOPS
0
1
Figure 45. Stereo Line Output
PMLO
Mode
LOUT/ROUT pin
0
Power-down
Pull-down to AVSS
1
Normal Operation
Normal Operation
0
Power-save
Fall down to AVSS
1
Power-save
Rise up to VCOM
Table 50. Stereo Line Output Mode Select (x: Don’t care)
Default
LOVL
Gain
Output Voltage (typ)
0
0dB
0.6 x AVDD
Default
1
+2dB
0.757 x AVDD
Table 51. Stereo Line Output Volume Setting
LOUT 1µF
ROUT
220Ω
20kΩ
Figure 46. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)
MS0543-E-00
- 56 -
2006/09