AK8452 Datasheet, PDF (6/46 Pages) Asahi Kasei Microsystems – 2 channel-input 16 bit 10MSPS ADC

ASAHI KASEI
AKM Confidential
[AK8452]
Circuit Block Description
„ Sensor Interface Part
Circuit to sample & hold input signal which is fed on CISIN pin. Signal input range is 1.98V
(typ.). There are two input modes, DC Direct Coupled Mode and CDS Mode. In DC Direct
Coupled Mode, Positive polarity signal is handled. In CDS Mode, Negative polarity signal is
handled. Signal Reference Voltage should be input on VCLP pin in DC Direct Coupled mode. In
CDS mode, Voltage level to clamp signal is internally generated and it is output on VCLP pin.
„ Black Level Correction Circuit
Circuit to add an offset voltage to the sampled signal level. Voltage range of DAC which
generates Offset is ±240 mV (typ.) and its resolution is 8 Bit.
„ PGA Part
Circuit to adjust signal amplitude, prior to AD conversion. Adjustable gain range is from 0dB to
13.9dB ( typ. ) (1.0× ~ 4.9×) and its resolution is 6 Bit.
„ ADC Part
AD conversion circuit to convert into Digital data an Analog signal after both Black level
correction and Gain adjustment are made. Its resolution is 16 Bit with its maximum conversion
rate of 10MSPS. Data output is in a straight Binary code. 0000h is output at Black level input
( 0Vpp input ) and FFFFh is output at White level input ( maximum input ).
„ Output Control Part
A 16 Bit-wide × 2ch ADC output data is re-arranged into 2 Bit × 8 cycle×2ch or 4Bit × 4cycle×2ch
stream at this part. In Single Edge Mode operation, Data is output at the rising edge of MCLK.
In Double Edge Mode operation, it is output at both rising and falling edges of MCLK. Output
mode is 2bit or 4bit by single mode, only 2bit on double mode. Particulars is on P35 ~ P37.
„ Reference Voltage Generator
Circuit to generate internal reference voltages. Clamp Reference Voltage VCLP, internal
common voltage VCOM and ADC reference voltages VRP and VRN are generated. Each
reference voltage is output on respective device pins. For voltage stabilization, capacitors should
be connected between respective pins and AVSS.
„ LED Driver Part
This product generates has 3 channel LED driver to drive RGB constant current. Use the ON/
OFF digital terminal to control the constant current.
„ Serial Interface Part
A 3-Wire Interface circuit to access setting-registers. SDCLK (clock) and SDATA (data) pins are
shared with D0 and D1 pins of ADC Data Output. When SDENB pin is at low, D0 and D1pins
function as SDCLK and SDATA input pins. In order to avoid both SDCLK and SDATA pins to
become floating condition, proper pull-down resistors should be connected between D0 / SDCLK
pin, D1 / SDATA pin and AVSS respectively.
MS0955-E-00
6
2008/03