AK8452 Datasheet, PDF (28/46 Pages) Asahi Kasei Microsystems – 2 channel-input 16 bit 10MSPS ADC

ASAHI KASEI
AKM Confidential
PGA0 gain setting ( address “0010”, reset “xx00 0000”）
register
000000
000001
000010
000011
:
:
111100
111101
111110
111111
Gain(x) = ^1.98 × ⁸⁰ [times]
2.0 16 + (63 − x)
@ reset x=0, Gain(0)=1.0 times
5
Gain [ times ]
1.003
1.015
1.029
1.042
:
:
4.168
4.400
4.659
4.950
; x is setting value
0.5
4
0.4
3
0.3
2
0.2
1
0.1
0
0
0
16
32
48
64
setting value [DEC]
gain curve (theoretical figure)
[AK8452]
gain[times]
step[times]
** The definition with the above PGA gain is the value of PGA simple substance. In DC direct mode, ( the
positive-polarity ) is gained < PGA gain's being duple > after offset adjustment in the voltage of the
difference between the reference voltage which is inputted to the VCLP terminal and the signal level ( the
part of SHD ). In CDS mode , ( the negative electrode ), the voltage of the difference between the reference
level ( the part of SHR ) and the signal level ( the part of SHD ) is gained absolute gain duple(-0.6dB typ.)
and it is < PGA gain's being duple > after offset adjustment.
MS0955-E-00
28
2008/03