AK8452 Datasheet, PDF (19/46 Pages) Asahi Kasei Microsystems – 2 channel-input 16 bit 10MSPS ADC

ASAHI KASEI
AKM Confidential
[AK8452]
„ Serial interface: Switching characteristics
( AVDD=3.135~3.465V, DRVDD=3.0~3.6V ,Ta= 0~70°C , unless otherwise specified)
No.
Item
pin
Min. Typ. Max. unit Condition
1 Clock Period
SDCLK 0.1
10 MHz
2 Clock Pulse Width (H duration) SDCLK
40
ns
3 Clock Pulse Width ( L duration ) SDCLK
40
ns
4 SDENB setup time
SDENB
80
ns
(to SDCLK rising edge↑)
5 SDENB hold time
SDENB
80
ns
(from SDCLK rising edge↑)
6 Data High-Z delay
D0, D1
0
(from SDENB falling edge↓)
40 ns
7 Data Enable delay
(from SDENB rising edge↑)
D0, D1
0
40 ns
8 SDATA setup time
SDATA
40
ns
(to SDCLK rising edge↑)
9 SDATA hold time
SDATA
40
ns
( from SDCLK rising edge↑)
SDENB
10 SDCLK,SDENB Rise time
SDCLK
SDENB
6
ns
11 SDCLK,SDENB Fall time
SDCLK
SDENB
6
ns
12 SDENB High level pulse width SDENB
40
ns
SDENB
0.7AVDD
0.3AVDD
11
6
D0
4
SDCLK
6
D1
1
0.7AVDD
0.3AVDD
10
3
11
2
0.7AVDD
0.3AVDD
10
5
12
7
0.7DVDD
0.3DVDD
7
0.7DVDD
0.3DVDD
SDATA
0.7AVDD
0.3AVDD
8
9
Serial interface timing
Clock Input pin SDCLK and Data Input pin SDATA for Serial Interface are shared with A/D
Data Output pins, D0 and D1 respectively. When SDENB becomes low, D0 and D1 are put into
High-Z conditions and it is enabled to input SDCLK and SDATA. SDATA is captured at the
rising edge of SDCLK. SDATA is 16 Bit long. Write “zeros“ first bit and from the 5^th Bit to the 5^th
Bit. 2^nd~4^th Bits are assigned for Register Address where the 2^nd Bit is MSB and the 4^th Bit is
MS0955-E-00
19
2008/03