AK8181A Datasheet, PDF (6/8 Pages) Asahi Kasei Microsystems – 3.3V LVPECL 1:4 Clock Fanout Buffer

AK8181A
Function Table
The following table shows the inputs/outputs clock state configured through the control pins.
CLK_EN
0
Table 1: Control Input Function Table
Inputs
CLK_SEL
Selected Source
Q0:Q3
Outputs
Q0n:Q3n
0
CLK0
Disabled: Low
Disabled: High
0
1
CLK1
Disabled: Low
Disabled: High
1
0
CLK0
Enabled
Enabled
1
1
CLK1
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 7. In the active mode, the state of the outputs is a function of the CLK0 and CLK1 as
described in Table 2.
CLK0, CLK1
Disabled
Enabled
CLK_EN
Q0n : Q3n
Q0 : Q3
Figure 7 CLK_EN Timing Diagram
Table 2 Clock Input Function Table
Inputs
CLK0 or CLK1
Q0 : Q3
Outputs
Q0n : Q3n
0
Low
High
1
High
Low
Nov-2011
MS1342-E-00
-6-